1. Field of the Invention
Exemplary embodiments of the present invention relate to a phase locked loop (PLL); and, more particularly, to a PLL and a satellite communication terminal using the same.
2. Description of Related Art
A PLL refers to a circuit which obtains a stable oscillation output having a frequency equal to that of a reference signal or a divided or multiplied frequency of the reference signal. The PLL serves as a local oscillator which allocates a channel or converts a frequency into a radio frequency (RF) or an intermediate frequency (IF) in a wireless communication system.
FIG. 1 is a block diagram illustrating a structure of a PLL.
Referring to FIG. 1, the PLL 100 includes a phase detector 101, a charge pump 103, a loop filter 105, a voltage controlled oscillator (VCO) 107, and a frequency divider 109.
The phase detector 101 detects a phase difference between a reference frequency fr and a division frequency fo/N outputted from the frequency divider 109, and outputs a signal corresponding to the detected phase difference. Generally, a reference frequency fr is generated using a temperature compensated X-tal oscillator (hereinafter, referred to as a TCXO) which is stable with respect to temperature change.
The charge pump 103 converts an output signal of the phase detector 101 into a voltage level.
The loop filter 105 accumulates charges from the charge pump 103 and discharges the accumulated charges, and filters noise containing unnecessary high frequency components. Generally, the loop filter 105 has a low pass filter (LPF) structure.
The VCO 107 outputs a frequency fo which is proportional to an inputted voltage.
The frequency divider 109 divides the frequency fo from the VCO 107 by a frequency division ratio N, and outputs the division frequency fo/N which is phase-compared with the reference frequency fr by the phase detector 101.
Phase noise refers to unnecessary energy which is not a signal component and appears around a desired frequency such as an oscillation frequency or a carrier frequency. Since such phase noise characteristic of the PLL affects the performance of the overall system, phase noise must be reduced.